8-bit Shift Register Design

Description:

We are going to perform the design of a 8-bit shift register that has serial-in/parallel-out and parallel-in/parallel-out operations 
based on a ‘select’ signal that is being specified as an input.

PART 1: SCHEMATICS

1. The first thing I did was create a D-FLIP FLOP using transmission gates and inverters. To make the design easier to look at, I created individual cells for the inverter and the transmission gate and made symbols for them.

Why a D-FLIP FLOP?

I am using D flip-flops as the core storage elements for the 8-bit shift register because they provide a simple, reliable, and clock-controlled way to store and transfer data. A D flip-flop captures the value of the input D on the rising edge of the clock and holds it at the output Q until the next clock edge, making it ideal for sequential logic and data shifting.

Inverter schematic and symbol:

Transmission gate and schematic and symbol:

D-Flip-Flop symbol using transmission gate symbol and inverter symbol: 

I created the D flip flop using the symbols I made previously. I used Clk and Clk’ as my inputs. I inverted Clk using an inverter. I made this D flip flop symbol omitting the Clk’ as a pin because we do not need it after this step. The symbol has a triangle on top to show that it is edge triggered. The D pin is an input/output pin since we will be using it as both an input and output since we are cascading D flip flops.

Individual D-Flip-Flop simulation

 I simulated the individual D flip flop first to make sure that it works. I used two input pulses, D and Clk with values listed below. I used a shorter delay for the clock because the clock should be on before D turns on. I did not look at Q’ in this simulation because it’s result is the inverse of Q. The result of Q shows that the D flip flop works since it pulses on at the rising edge of clock. The “on” pulse of Q corresponds to the “on” signal of D at the rising edge of Clk. This shows that the individual D flip flop works.

SHIFT REGISTER:

The design of the 8-bit shift register will use multiple 2:1 MUX to select between the serial-in/parallel-out and parallel-in/parallel-out. There are ouputs D<0:7> and inputs P<0:7>. Among this inputs there is the serial input that is P0. There are also present a CLK pin and the S(select) pin. The select pin will select what input to use, parallel-in(select=1) or serial-in(select=0).

SHIFT REGISTER SIMULATIONS:

Parallel input:

Select:1 Word:11111111

Select:1 Word: 10111110

Select:1 Word: 00000000 

Serial Input:

Select: 0 Word: 11010011 

Select: 0 Word: 10001000

Select: 0 Word: 01010101

LAYOUTS AND SIMULATIONS:

Layout for storage element(D-Flip-Flop):

Layout:

DRC:

LVS:

Layout for 8-bit shift register:

Layout:

DRC: