A report on design 8-bit manchester adder

Table of contents

1. Abstract
2. Requirement for the 8-Bit Adder Project
3. Circuits for a 8-Bit Manchester Adder
4. 1 Bit Adder Configuration and Testing
5. 8-Bit Manchester Adder Configuration and Testing
6. Power Estimation
7. Adder Architecture Comparison

1.Abstract

Addition is one of the most fundamental and frequently used arithmetic operations in digital systems, often forming the critical path in performance-limited applications. Therefore, optimizing the adder design is crucial for improving overall circuit speed and efficiency. For EE456 Project 1, the goal is to design an 8-bit Manchester carry chain adder using static logic, to be implemented as part of the accumulator section in a high-performance chip under development for Letni Corporation.

In this project, we focus on reducing propagation delay and improving throughput, while maintaining a compact layout area. Among various logic families, we opt for a static CMOS logic style, leveraging its robustness and noise immunity for high-speed applications.

Our design approach begins with the analysis of the fundamental building blocks of the Manchester adder, such as the carry chain (C-chain) and the XNOR gate, for which we employ a mirror circuit configuration. We first validate the transistor-level design of a 1-bit static Manchester adder through pre-layout schematic simulations. This unit is then scaled to an 8-bit adder, and its performance is evaluated in terms of timing and functional correctness.

2.Requirements for the 8-Bit Adder Project

Description of the Project

Performance Measures

Area(A), Time(T), Power(P), or AT² can be selected as circuit performance.  Initially specification and optimization of the design goal are required.

Clock rise and fall signals are assumed to be of 0.1nsec.

Optimization Techniques 

Different optimization techniques we use to achieve above goals are listed below: 

• Logic-level optimization 
• Transistor sizing 
•  Progressive Transistor Sizing 
• Transistor ordering 
• Layout Consideration 

Transistors minimum size

NMOS transistor size: W_n/L_n = 120nm/45nm

We assume Wp = 1.5Wn

PMOS transistor size: W_n/L_n = 180nm/45

This sizing balances the difference in carrier mobility between NMOS and PMOS transistors, as electrons (NMOS) move faster than holes (PMOS). By making the PMOS 1.5 times wider, we achieve similar rise and fall times, improving signal symmetry and timing. These sizes also minimize area and power while maintaining functional performance for basic CMOS logic gates.

3.Circuit for a 8-Bit Manchester Adder

Objective: Design a high speed 8-bit Manchester Adder

Circuit configuration

I will structure the 8-Bit Manchester Adder circuit as a combination of three main blocks: PG block, C-Chain block, and Sum block.

Figure 1. Adder Circuit Configuration

PG Block

In the PG block, Pi (propagation) and Gi(generation) can be obtained by the functions below:

P_i = A_i  ⊕ B_i         Propagate carry C_o

G_i = A_i · B_i         Generate carry

D_i = A̅ · B̅         Delete Carry

C-Chain block Circuit Characteristics and Simulation

The C-Chain is constructed in Figure 3. The carry-propagation circuitry for  C_i = AB + BC_i + AC_i can be simplified by adding generate and delete signals, as shown in Figure 3. The propagate path is unchanged, and it passes C_i to  the C_o output if the propagate signal P_i is true. If the propagate condition is not satisfied, the ouput is eiter pulled low by the D_i signal or pulled up by G̅_i. It can be observed that the transistor level implementation does not have the delete D_i signal and instead it has the signal G̅_i in series with P̅ since D can be obtained combining G and P.

Figure 2. Manchester carry chain implemented using Transmission gate and CMOS technology

Figure 3. Schematic at transitor level of the C-Chain Circuit 

Simulation setup:

C_in : 01010101

G : 00000011

P :00111100

Figure 4. C-Chain simulation analog and digital

Sum Block

The function of Sum is S_i = P_i + C_i-1. Its implementation is very simple, so the simulation result is omitted here.

XNOR Circuit Design and Simulation

Due to request for faster and/or more compact circuit structures, the mirror circuit is selected here to implement XNOR, in which the N-MOS and P-MOS arrays have exactly the same structure and have the same characteristics as series-parallel logic formation and easy to layout. Figure 5 shos the XNOR mirror circuit. This circuit is of interest because it has shorter switching time. 

Figure 5. XNOR mirror circuit

For optimal propagation delay and power comsumption the transistor sizes are set to x2 the minimum size. Wn = 240nm and Wp = 360nm.

Figure 6. XNOR schematic

Simulation setup:

A: 0011

B: 0101

Figure 7. XNOR simulation setup, parameters and results

The simulation results in Figure 7 recreate the XNOR logic perfectly so the implementation is correct.

NAND Circuit Design and Simulation

The NAND logic functionality will be implemented using CMOS logic, following the design studied in class and outlined in Figure 8. The implementation will not follow the size ratios shown in Figure 8. Instead Wp = 360nm and Wn = 240nm. 

Figure 8. NAND design using CMOS technology

Figure 9. NAND schematic, simulation and results

The simulation results display the input waveforms for A and B, along with the corresponding output signal, OUT. As observed, the output behavior aligns with the expected NAND truth table, confirming the correct functionality of the CMOS implementation.

4. 1 Bit Adder Configuration and Testing

With all necessary building blocks for the 8-bit Manchester Adder successfully designed and verified, the next step involves presenting and testing the implementation of the 1-bit Adder. This serves as a foundation before progressing to the complete 8-bit Manchester Adder design.

Structure and Simulation of 1 Bit Adder

Figure 10. 1-Bit Adder schematic, simulation and results

The simulation results confirm that the adder accurately performs the binary addition of inputs A and B, validating its correct functionality.

5. 8-Bit Manchester Adder Configuration and Testing

Figure 11. 8-Bit Adder schematic

Figure 12. 1-Bit Adder Simulation Setup

Figure 13. 8-Bit Adder Simulation Results

6. Power Estimation

Method used

For this report the power dissipated by the 8-Bit Adder is evaluated using a fixed set of predefined input vectors.  This controlled approach provides insight into how the adder behaves under specific input patterns and allows us to verify functionality while observing power consumption behavior in a more deterministic environment.

Each vector pair was applied for 1 ns using a .vec file in Virtuoso ADE Explorer, synchronized with a 1 GHz clock signal generated by a vpulse source with rise and fall times of 100 ps and a pulse width of 0.5 ns.

Power Measurement Methodology

Figure14. 8-Bit Adder Power Estimation

To measure the average power consumption:

1. The power supply was modeled using a 1.2 V DC source connected to the vdd net of the circuit.

2. The total current drawn from this supply was probed.

3. In the ADE Explorer calculator, power was computed using the expression:

average((- (IT(/V0/PLUS) * VT(/vdd!))))

Results

The average power dissipation of the 8-bit Manchester carry-chain adder was measured to be 52.32 µW in the pre-layout simulation. This value is considered low and reflects the simplicity and efficiency of the adder’s architecture. Since the Manchester adder operates sequentially with minimal switching activity and no complex routing, it consumes significantly less power compared to parallel prefix adders. This makes it well-suited for low-power applications where speed is not the primary constraint.

7.Adder Architecture Comparison

This section presents a comparison between the implemented 8-bit Manchester carry-chain adder and four widely used parallel prefix adder architectures: Kogge-Stone, Brent-Kung, Han-Carlson, and Ladner-Fischer. The comparison focuses on four key design parameters: power consumption, logic depth, fan-out, and layout complexity.

The Manchester adder is a simple and compact structure with low area and minimal wiring, making it well-suited for small-scale and low-power applications. However, its linear logic depth results in longer delay compared to prefix-based designs. Parallel prefix adders, such as Kogge-Stone and Ladner-Fischer, offer significantly faster computation through logarithmic depth but require more complex routing and consume higher power. Brent-Kung and Han-Carlson adders represent optimized trade-offs, balancing area, speed, and wiring overhead.

The following tables summarize the characteristics and relative performance of each architecture.

Table1. Power Comparision Table

Table2. Logic Depth Comparison Table

Table3. Fan-out Comparison Table

Table4. Area and Layout Complexity Comparison Table

8.Layouts

Inverter:

Figure 15. Inverter Layout, DRC and LVS

C_Chain Layout:

Figure 16. C-Chain Layout, DCR and LVS

XNOR gate:

NAND:

1-Bit-Adder: