Transistor-Level Design of a Low-Power 8×8 Vedic Multiplier in 45nm CMOS Technology

Student Name: Alejandro Barroso
Course: ECE 45600 
Project: Project 2 – 8x8 Bits Multiplier Design
Date: April 8, 2025

Abstract

This project presents a transistor-level implementation of an 8×8-bit digital multiplier using the Urdhva Tiryagbhyam sutra from Vedic Mathematics. Designed in 45nm CMOS technology, the proposed architecture aims to optimize power consumption and speed for future-generation RISC processors. The multiplier is structured by combining four 4×4 Vedic blocks with ripple carry adders for partial product summation. Analytical estimates predict significant reductions in propagation delay and average power dissipation compared to Wallace Tree and Array multipliers. Preliminary results suggest an average power dissipation of approximately 40-45 µW and a worst-case delay of 0.3-0.5 ns, using a nominal supply of 1.2 V. The estimated maximum clock frequency is approximately 3–4 GHz. Cadence simulations and performance evaluation are ongoing.